Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.
A typical flash memory comprises a memory array, which includes a large number of memory cells arranged in blocks. The flash memory is differentiated from other non-volatile memory in that flash memory cells can be erased and reprogrammed in blocks instead of one byte at a time.
The memory blocks each have a row or X-decoder. A column or Y-decoder is shared by multiple memory blocks. An example of a typical memory block architecture is illustrated in FIG. 1. This architecture uses an X-decoder for each block of memory.
FIG. 1 shows two columns 120 and 121 of memory blocks. Each column 120 and 121 is comprised of eight flash memory array blocks 110–115. Each memory array block 110–115 has a dedicated X-decoder 101–106 respectively. Additionally, each column 120 and 121 has a sense amplifier 130 and 131 that is coupled to a sense amplifier driver 140 and 141.
In order for memory manufacturers to remain competitive, memory designers must constantly increase the density of flash memory devices. This is typically accomplished by reducing the size of the flash memory arrays. The size of the address decoder (e.g., X-decoder, Y-decoder), however, is not shrinking. In fact, as the memory array size is reduced, the proportion of the die that is made up of X-decoders increases. This ultimately limits amount of memory arrays that can fit on one die.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a memory array architecture that reduces the amount of die space occupied by address decoders.